ESPRIT '88: Putting the Technology to Use : Proceedings of the 5th Annual ESPRIT Conference, Brussels, November 14-17, 1988, Part 1North-Holland, 1988 - 1759 pages Part1. Advanced microelectronics. VLSI technologies - comparisons and prospects. Software technology. Advanced information processing. Part2. Office systems.Computer integrated manufacturing. Information exchange system. |
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Page 204
... LFSR that must be of length < 20 bits so that it can be run through its full sequence . In the case where the LFSR and the block of logic have the same number of bits then each input vector will be applied once only as for classical ...
... LFSR that must be of length < 20 bits so that it can be run through its full sequence . In the case where the LFSR and the block of logic have the same number of bits then each input vector will be applied once only as for classical ...
Page 205
... LFSRs are capable of generating a maximal length sequence when generating patterns in parallel . However , the rule is not easy to use because it gives chip designers a limited number of pairs of LFSR lengths they can use . Also , the ...
... LFSRs are capable of generating a maximal length sequence when generating patterns in parallel . However , the rule is not easy to use because it gives chip designers a limited number of pairs of LFSR lengths they can use . Also , the ...
Page 212
... LFSR with a length of at least 10 bits and not greater than 20 bits . The data inputs are connected to a single LFSR with no upper limit on its length . The write enable signal is connected to an LFSR with no upper length limit . The ...
... LFSR with a length of at least 10 bits and not greater than 20 bits . The data inputs are connected to a single LFSR with no upper limit on its length . The write enable signal is connected to an LFSR with no upper length limit . The ...
Contents
A Technology Transfer from Research to Development Project | 3 |
BitRate Reduction of High Quality Audio Signals Using FloatingPoint | 13 |
Materials and Devices Toward ThreeDimensional Integration Project 245 | 22 |
Copyright | |
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Common terms and phrases
abstract algorithm allows analysis Aphrodite application approach architecture array basic behaviour BICMOS cell chip circuit CMOS communication complex components Computer concepts constraints database debugging defined demonstrator described devices distributed domain dynamic efficient environment error Esprit Project etching evaluation example execution expert systems Figure function GaAs gate GEODE global goal graphical IEEE implementation inference engine input integrated integrated circuits interaction interpreter kernel knowledge base knowledge representation layer LFSR logic programming machine mechanism memory MESFET method methodology module node object-oriented objects operations optimization output parallel parameters partial evaluation PCTE performance phase possible predicates problem Proc procedure processor Prolog Prolog III prototype query relations representation requirements rule semantic sequence signal simulation specific structure subcircuit SUPERNODE task techniques transistor transputer tuple UNIX VLSI wafer