ESPRIT '88: Putting the Technology to Use : Proceedings of the 5th Annual ESPRIT Conference, Brussels, November 14-17, 1988, Part 1North-Holland, 1988 - 1759 pages Part1. Advanced microelectronics. VLSI technologies - comparisons and prospects. Software technology. Advanced information processing. Part2. Office systems.Computer integrated manufacturing. Information exchange system. |
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Page 75
... gate - length ( figure 6 ) . These devices show a gate leakage of 40 nA at -5 V , transconductance of 140 mS / mm and a gate capacitance of 1.2 pF / mm ( -2 V bias ) . The transit time , given by the ratio Cg / gm , is 14 ps . Diffused ...
... gate - length ( figure 6 ) . These devices show a gate leakage of 40 nA at -5 V , transconductance of 140 mS / mm and a gate capacitance of 1.2 pF / mm ( -2 V bias ) . The transit time , given by the ratio Cg / gm , is 14 ps . Diffused ...
Page 79
... gate delay times of < 100 ps and the integration of 25 K gates in an area of about 150 mm2 . Therefore it is necessary to reduce the minimum structure size to 1 um to develop a suitable transistor structure and a multilayer ...
... gate delay times of < 100 ps and the integration of 25 K gates in an area of about 150 mm2 . Therefore it is necessary to reduce the minimum structure size to 1 um to develop a suitable transistor structure and a multilayer ...
Page 257
... gate array design system maps logic in a technology independent manner onto a gate array or a sea - of - gates . Availability : the programs are available as alpha site prototypes . They are presently being coupled to the ASTRA ...
... gate array design system maps logic in a technology independent manner onto a gate array or a sea - of - gates . Availability : the programs are available as alpha site prototypes . They are presently being coupled to the ASTRA ...
Contents
A Technology Transfer from Research to Development Project | 3 |
BitRate Reduction of High Quality Audio Signals Using FloatingPoint | 13 |
Materials and Devices Toward ThreeDimensional Integration Project 245 | 22 |
Copyright | |
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abstract algorithm allows analysis Aphrodite application approach architecture array basic behaviour BICMOS cell chip circuit CMOS communication complex components Computer concepts constraints database debugging defined demonstrator described devices distributed domain dynamic efficient environment error Esprit Project etching evaluation example execution expert systems Figure function GaAs gate GEODE global goal graphical IEEE implementation inference engine input integrated integrated circuits interaction interpreter kernel knowledge base knowledge representation layer LFSR logic programming machine mechanism memory MESFET method methodology module node object-oriented objects operations optimization output parallel parameters partial evaluation PCTE performance phase possible predicates problem Proc procedure processor Prolog Prolog III prototype query relations representation requirements rule semantic sequence signal simulation specific structure subcircuit SUPERNODE task techniques transistor transputer tuple UNIX VLSI wafer