ESPRIT '88: Putting the Technology to Use : Proceedings of the 5th Annual ESPRIT Conference, Brussels, November 14-17, 1988, Part 1North-Holland, 1988 - 1759 pages Part1. Advanced microelectronics. VLSI technologies - comparisons and prospects. Software technology. Advanced information processing. Part2. Office systems.Computer integrated manufacturing. Information exchange system. |
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Page 270
... subnetworks and analyzing each subnetwork separately is a well known technique to reduce complexity . Several verification programs divide a circuit into connected components ( DCN ) [ 6 ] , [ 7 ] . In this way , the interaction between ...
... subnetworks and analyzing each subnetwork separately is a well known technique to reduce complexity . Several verification programs divide a circuit into connected components ( DCN ) [ 6 ] , [ 7 ] . In this way , the interaction between ...
Page 294
... subnetwork . In 7a , there is a time interval during which an unintended state can ' slip ' through the latch , because the condition signal A is not stable in time . In the case of 7b , the output of the precharged gate may discharge ...
... subnetwork . In 7a , there is a time interval during which an unintended state can ' slip ' through the latch , because the condition signal A is not stable in time . In the case of 7b , the output of the precharged gate may discharge ...
Page 613
... subnetwork is not blocked , then an applicable rule will be found by the controller and applied . Remark : Without fairness requirement , the interpreter would be much more simpler since the controller would only have to check the ...
... subnetwork is not blocked , then an applicable rule will be found by the controller and applied . Remark : Without fairness requirement , the interpreter would be much more simpler since the controller would only have to check the ...
Contents
A Technology Transfer from Research to Development Project | 3 |
BitRate Reduction of High Quality Audio Signals Using FloatingPoint | 13 |
Materials and Devices Toward ThreeDimensional Integration Project 245 | 22 |
Copyright | |
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Common terms and phrases
abstract algorithm allows analysis Aphrodite application approach architecture array basic behaviour BICMOS cell chip circuit CMOS communication complex components Computer concepts constraints database debugging defined demonstrator described devices distributed domain dynamic efficient environment error Esprit Project etching evaluation example execution expert systems Figure function GaAs gate GEODE global goal graphical IEEE implementation inference engine input integrated integrated circuits interaction interpreter kernel knowledge base knowledge representation layer LFSR logic programming machine mechanism memory MESFET method methodology module node object-oriented objects operations optimization output parallel parameters partial evaluation PCTE performance phase possible predicates problem Proc procedure processor Prolog Prolog III prototype query relations representation requirements rule semantic sequence signal simulation specific structure subcircuit SUPERNODE task techniques transistor transputer tuple UNIX VLSI wafer